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Synthesizable SystemVerilog for an FPGARTL Engineer
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 3.68 GB | Duration: 12h 5m
Using Xilinx Vivado Design Suite 2020
What you'll learn
Fundamentals of SystemVerilog Programming that will help to ace RTL Engineer Job Interviews.
Understand Vivado Design Suite flow for Digital System Design.
Different Modelling Styles in Hardware Description Language.
How to use Xilinx IP's and create Custom IP's.
IP integrator Design flow of the Vivado.
Writing Verilog Testbenches.
Design of some real world projects such as : PMOD DA4 DAC interface, Function Generator, Small Processor Architecture, UART Interface, PWM, BIST for Development boards and many more.
Requirements
Fundamental of Digital Circuit will give an added advantages.
Description
FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. SystemVerilog plays the dominant role in the Verification Domain as well as RTL designing. The best part about both of them is once you know SystemVerilog you automatically understand the VHDL and then the capabilities of both worlds can be used to build complex systems. The course focus on the Synthesizable SystemVerilog constructs help to build RTL that can be tested on the FPGA Hardware. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.
The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite 2020 along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.
Who this course is for
VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.
Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ SystemVerilog Hardware Description Language
Anyone interested to start career in ASIC/ VLSI domain.
https://www.udemy.com/course/synthesizable-systemverilog-constructs-for-rtl-design/
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