Fundamentals of Verification and System Verilog
Fundamentals of Verification and System Verilog
Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: aac, 44100 Hz
Language: English | Size: 6.04 GB | Duration: 7 section | 49 lectures | (21h 42m)
What you'll learn
Significance of verification
Verification options, methodologies, approaches and plan
Examples to practice on verification tool EDA Playground
Testbench Fundamentals
Writing your SystemVerilog code
Various SystemVerilog Data Types including User Defined Data Types
Procedural Statements
Interface Concepts
Requirements
Verilog programming and fundamentals of FPGA programming are supposed to be already known
Familiarity with C and C++ will be an added advantage
Knowledge of digital circuit design
Description
This course is introduced for learners who wants to learn fundamental concepts of Verification and basic concepts of SystemVerilog. It is assumed that learner is aware of the Verilog hardware description language. In this course, learners will be introduced to why verification is to be done and what is verification. One of the verification language SystemVerilog constructs will be introduced. Layered testbench and its various components will be discussed. Learner's will also be introduced to various data types, procedural control statements and interfaces in SystemVerilog. Course is being taught with various examples and learner can monitor self-progress by attempting quiz and assignment in each section.
Who this course is for:
This course is for students and engineers who wants to learn basics of verification and basic constructs of SystemVerilog
Verification engineers who wants to refresh concepts of SystemVerilog
Job seekers in verification industry
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