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Cadence XCELIUM 20.03.017 Linux

Cadence XCELIUM 20.03.017 Linux
Free Download Cadence XCELIUM 20.03.017 | 16.9 Gb
Owner:Cadence
Product Name:XCELIUM
Version:20.03.017 (XCELIUMMAIN) *
Supported Architectures:x86_64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:Linux *
Size:16.9 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability ofXCELIUM 20.03.017 (XCELIUMMAIN)is part of the Cadence Verification Suite and supports the company's Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.





CCRID Product Title
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AVSREQ-111477 PROBE Probe command should be graceful for missing instances/exclude signals/exclude hierarchies
AVSREQ-110516 SPECMAN_OTHER_LANGUAGES FLI: conflicting types for 'bool' when user uses FLI manager
AVSREQ-110428 DMS_ELAB AMS test case with SV interface to Spice fails when using -ms_perf for multi-supply
AVSREQ-110131 ELAB_DOC Incorrect switch XELPSA given in cdnshelp documentation
AVSREQ-109792 UVM_ML UVM ML is calling xcelium -save_process_mode=ON which is redundant when using the new process_save method
AVSREQ-109790 ASSERTION_SVA Compilation error with tool generated conditional waiver file
AVSREQ-109595 SPECMAN_SAVE_RESTORE xrun restore sndynload fail
AVSREQ-109475 GLS_TIMING DEFAULT line in tfile doesn't seem to take list of tcheck as part of -tcheck
AVSREQ-109178 SPECMAN_E Internal error passing an enum parameter using FLI
AVSREQ-108312 SV_CODEGEN xmvlog_cg internal error with MESSAGE: gq_e_class_select - vxt_vxl unflagged!
AVSREQ-108259 JUPITER_ENGINE Internal Error during South compilation
AVSREQ-107822 CORE_RAND backdoor fails when constraints are specified hierarchically and part of constraint object is queue
AVSREQ-107753 MSIE_ELAB Result of -genpartition is a strongly biased distribution
AVSREQ-107712 CORE_RAND Support constraints on queues in backdoor
AVSREQ-107642 JUPITER_GLST MC internal exception, while handling GLST
AVSREQ-107538 ELAB_SV Enhancing conditional operator to handle partial known constant and give warning for appropriate branch
AVSREQ-107343 XUFE_V2V_VST illegal $width statement generated with MC when module in NACC
AVSREQ-107313 JUPITER_ENGINE cpu_affinity.log is growing during the entire simulation
AVSREQ-107250 GLS_PERFORMANCE -enctran gives an internal exception with -ctransmall 0
AVSREQ-107165 ELAB_SV PRPSWM warning post-rebase when -createdebugdb is used
AVSREQ-107148 ELAB_BIND relax_svdupi has no effect
AVSREQ-107126 DEPRECATE_CORE_LP Low Power simulation Reporting *E , NOCNINP for PG PIN
AVSREQ-106975 MULTI_CORE_COMPILER Edits to stdout during XUFE run have removed ALL references to MultiCore
AVSREQ-106959 SIM_LICENSE Xcelium safety license is available but is not picked and gives lic_error -5
AVSREQ-106733 SIM_USABILITY Open xm.db file related to a pak file with O_RDONLY permission during simulation
AVSREQ-106689 ASSERTION_SVA INTERR vxt_ec_rvalue - D default - 553 - $assertoff with path argument
AVSREQ-106667 CORE_PARSE_SV macro parsing fails with E,NULLEI
AVSREQ-106645 IXCOM instance array error with xmelab in ixcom flow with upf and liberty file
AVSREQ-106622 JUPITER_GLST The backwalk is not working when tsmc_xbuf is present
AVSREQ-106617 CORE_SV_IN Internal error related to -ENABLE_VIF_UNINST
AVSREQ-106615 VPI_GENERAL Indago becomes unresponsive on displaying annotations in interactive mode; simvision does not
AVSREQ-106030 ELAB_SV Using compile switch -enable_rswt causes Xcelium to throw internal error during elaboration
AVSREQ-105980 SPECMAN_ERRORS final error on inline error in 19.09 at elib link
AVSREQ-105911 JUPITER_COMPILER GLST: Internal exception during splitting
AVSREQ-105853 LP_1801 sv_seghandler - trapno -1 addr((nil)) with basic code
AVSREQ-105653 SIM_MLTYPEMAP MLLIBPCKSZ UVM_ERROR unpacking a class with static array field
AVSREQ-105616 JUPITER_BRIDGE -enable_frcrelconcatopt is causing too large code generation in MultiCore flow
AVSREQ-105590 COVERAGE_CODE xmsim INTERR sv_seghandler with vector scoring
AVSREQ-105345 LP_1801 LP elab performance is 8.5hr - 4x slower than non LP
AVSREQ-105344 LP_1801 LP runtime is 10x slower than non LP - Stream isolation input/device stream
AVSREQ-104971 ASSERTION_SVA ASSERTION: Support of bit select of concatenation
AVSREQ-104962 GLS_GENERAL Different result between Xcelium 19.12-a001 and 18.09-t001 on "always" processing
AVSREQ-104960 ELAB_SV No warning from -ii_wwarn for NBA assignment
AVSREQ-104851 SIM_SV_VHDL xmsim internal exception: MESSAGE: sv_seghandler - trapno -1 addr(0x200) when using $xm_mirror in TB
AVSREQ-104814 XPROP_GENERAL Unexpected 0 to x change in XPROP simulation while using 19.11.v001
AVSREQ-104754 ELAB_SV Elaboration internal error after solving mem issue
AVSREQ-104633 LP_1801 Xcelium 19.03.s013 internal exception on elaboration after adding -lps_dbc switch
AVSREQ-104591 XPROP_GENERAL Unexpected X from x-prop block
AVSREQ-104571 MSIE_ELAB Internal error, sv_seghandler - trapno -1 addr((nil))
AVSREQ-104550 MSIE_PERFORMANCE simulation performance -port_acc_optm under simperf
AVSREQ-104532 FUNC_SAFETY_SIM U in concurrent and D in serial
AVSREQ-104366 MSIE_ELAB MSIE incr error on _sv_export.c unknown type
AVSREQ-104328 SIM_PERFORMANCE reduce unification of streams with string parameter
AVSREQ-104270 ASSERTION_SVA internal error xut_term_rp_vep
AVSREQ-104190 MULTI_CORE_COMPILER MC_GLST_COMPILER: Process names for Splits being execute should be actual Split instances and not split_num
AVSREQ-104185 CORE_PARSE_SV sv preproc fails with mysterious error
AVSREQ-104170 MSIE_PERFORMANCE Supply type detection and information sharing across MSIE partitions
AVSREQ-104127 RAND_SOLVER RNDCNSTE error while using a rand variable as array index in a constraint
AVSREQ-104126 CORE_ELAB_PERF GLS Lynx11 performance issues
AVSREQ-104119 DEPRECATE_CORE_LP 2199222 CCR Unexpected NOCNINP for pg_pins of PA cells
AVSREQ-104068 MULTI_CORE_COMPILER Failure in south stage 4.16 - Create clock gater tree pes
AVSREQ-104027 XPROP_GENERAL Unexpected UNSXPC: Reg written in NBA has multiple drivers
AVSREQ-103983 SPECMAN_GUI 'wave exp' command with 'depth' option is not supported
AVSREQ-103956 VPI_GENERAL Unable to do a VPI read from C of the upper 32-bits of a 64-bit memory
AVSREQ-103932 SPECMAN_INTEF Port disconnect() Showing Error
AVSREQ-103913 SPECMAN_PERF Performance degradation between 18.03.016 and 19.03.011
AVSREQ-103873 SPECMAN_HAL OS Signal 11 at hal check
AVSREQ-103872 SPECMAN_COV Error during coverage data (ucd) creation with cross items
AVSREQ-103871 SPECMAN_E print -scale config setting does not affect time type with a bit modifier
AVSREQ-103848 SPECMAN_OTHER_LANGUAGES FLI glue code compilation fails when C declarations file includes another file
AVSREQ-103847 SPECMAN_E ELIB linking fails when method_ports instances of a TCM method_type are instantiated in different elibs
AVSREQ-103846 SPECMAN_COMPILE final compilation phase using elibs slowness
AVSREQ-103836 SPECMAN_COMPILE Compiling elib on top of precompiled specman executable affects shared object size
AVSREQ-103806 SPECMAN_UVM_E UVM low power UVC creator does not support CPF macro_models properly
AVSREQ-103789 UVM_ML_SYSC Ensure proper separation of design vs testbench SystemC entities for UVM-ML designs involving OSCI
AVSREQ-103691 SV_CODEGEN Internal exception error in elaboration
AVSREQ-103689 DEPRECATE_CORE_COVERAGE vector coverage on complex expression vectors is not appearing
AVSREQ-103688 DEPRECATE_CORE_LP Need support / enhancement w.r.t. "add_power_state command for Power Domain
AVSREQ-103632 MSIE_SIMULATION Unexpected behavior for msie flow with force
AVSREQ-103596 ELAB_SV xmupdate: *E,BUILDF error after reinvoking simulator
AVSREQ-103590 SPECMAN_UVM_E Unexpected abnormal status messages at the end of Specman eUnit tests
AVSREQ-103585 SPECMAN_GENERATION wrong source ref. in gen action error message
AVSREQ-103578 SPECMAN_OTHER_LANGUAGES FLI: bool type in e should be converted into C bool type
AVSREQ-103555 RAND_GENERAL Constraint failure on foreach with multidimensional array
AVSREQ-103468 DEPRECATE_SIM_GENERAL support for 'force' a field in packed struct
AVSREQ-102887 SPECMAN_SAVE_RESTORE Cannot open esv list file '/sn_permanent_files/snt_58332_7.esl' in the save restart flow
AVSREQ-102871 ASSERTION_SVA Xcelium Internal Error
AVSREQ-102780 SIM_PERFORMANCE Performance improvement request for the unknown checking function
AVSREQ-102743 MSIE_ELAB FCD support
AVSREQ-102734 DMS_ELAB ams_manual_segragation error with part select
AVSREQ-102639 SIM_PERFORMANCE 19.05 with/wo -linedebug the result is difference
AVSREQ-102631 DMS_AXUM multiple global supply voltages in the 'ie' SPCERR with xcelium 19 series and not with xcelium 18 series.
AVSREQ-102628 DMS_ELAB SOC level RTL DMS elaboration time internal error
AVSREQ-102619 SV_CODEGEN Elaboration fails in 19.08 with code generation errors on customer design
AVSREQ-102611 GLS_TIMING GLS Hold Timing Violation
AVSREQ-102608 SIMVISION_SCHEMATIC Failed to driver trace when -access enable
AVSREQ-102607 DMS_LP_AMS MS simulation internal error with esimAnalogEvent esimMixEureka.cc -> report error if -always_trigger used in MS designs
AVSREQ-102580 DMS_LP_AMS XPS MS simulation fails with internal exception
AVSREQ-102578 DMS_LP_AMS CPF level shifter expected on mixed signal boundary
AVSREQ-102575 SIMVISION_SCHEMATIC Change in Schematic Tracer behavior, SV interface signals are difficult to track
AVSREQ-102569 DMS_ELAB internal exception during platform elaboration : cu_connect_var_aca - bad type
AVSREQ-102557 DYNAMIC_TEST_SIMULATION [Dynamic Test] Getting INTERNAL EXCEPTION in Method SSS_MT_SVHASSIGN_ER_US
AVSREQ-102540 GLS_SDF unconditional TC annotated on conditional TC get conditional and odd behavior
AVSREQ-102537 DEPRECATE_ELAB_GENERAL xmelab fatal error illegal
AVSREQ-102528 IXCOM instance array error with xmelab in ixcom flow with upf and liberty file
AVSREQ-102525 DEBUG_PROBE Requirement to degrade the TCL probe Errors (ncsim: *E,DBOBBD) to Warnings
AVSREQ-102524 SV_GENERAL Give no ZROMCV message for Legal zero replication
AVSREQ-102520 SIM_SV_VHDL xm_mirror issue of SV packed array to VHDL array
AVSREQ-102499 GLS_GENERAL wrong SDFCTE warning with wrong instance checking
AVSREQ-102477 CORE_PARSE_PERF compile of tb taking 4x that of dut only
AVSREQ-102468 ELAB_BIND verilog config binding broke in 19.03-a001, which was propagated to 19.06.v001 at the rebase
AVSREQ-102461 ELAB_SV BNDWRN incorrectly generated for ternary assignment for localparam
AVSREQ-102458 COVERAGE_MERGING merge failing on generate block with module name and library name is the same in secondary where primary has worklib
AVSREQ-102456 ELAB_SV xmvlog_cg INTERR: gq_xf_fxtpointer - getting bigger is unexpected*
AVSREQ-102454 COVERAGE_CODE -primtops specified in single run MSIE mode is missing code coverage
AVSREQ-102447 COVERAGE_TOGGLE type name of parameterized module has same name even though parameters are different
AVSREQ-102442 RAND_GENERAL VM Randomize method call failed without any detailed info with multi-dimension Queue
AVSREQ-102434 CORE_PARSE_SV INFRA-558 Many topologies fail with SIGSEGV in xmvlog with xcelium agile 19.11.001
AVSREQ-102432 VPI_GENERAL Xcelium 19.07.001 - Agile release: uvm_reg peek on register field is not returning the proper value
AVSREQ-102430 VHDL_GENERAL *E,TRINDXC with -access
AVSREQ-102252 GLS_SDF xmelab INTERR with SDF file
AVSREQ-102214 SV_GENERAL xmelab: *E,CICAPC (<..>): incompatible or unsupported array port connection with -default_port_array_wire
AVSREQ-102196 DMS_AXUM Some instances specified in ie card are ignored when instance list is long
AVSREQ-102166 SV_GENERAL CUVDST Error - support for struct with .* port connection
AVSREQ-102158 VHDL_PARSE code compiles with Modelsim, but fails with Xcelium
AVSREQ-101475 COVERAGE_FSM Transition and state are not covered when arc coverage is enabled
AVSREQ-101344 SV_SYSC_ELAB Segmentation fault at elab time with message xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-101343 DOCUMENTATION Incorrect gcc version "4.8.3" mentioned in document "Installation and Configuration Information 18.09"
AVSREQ-101271 UVM_SV_CDNS_EXTENSIONS [CDNS/ASSERTION] extensions only supports ... error doesn't report source file/line
AVSREQ-101256 CORE_PARSE_SV Sparse directive is not properly handled when declaring several arrays in a comma separated list
AVSREQ-101138 ESW_ESWDBGEN Indago ESW becomes unresponsive due to unsupported tarmac format
AVSREQ-101136 ESW_ESWDBGEN eswd parallel run errors
AVSREQ-101115 MULTI_CORE_COMPILER cannot handle $random function to appear in the gate delay
AVSREQ-101064 ELAB_SV BNDWRN warning is reported when ternary operator(:?) is used but not reporting for case statement or if else.
AVSREQ-101036 DMS_LP_AMS xmelab internal exception with message xst_isprot - default
AVSREQ-100994 DEPRECATE_SIM_GENERAL $fclose() does not close filehandle
AVSREQ-100918 RAND_SOLVER xmsim: *W,SVRNDF and fatal RNDUNR after changing the tool version to 19.xx
AVSREQ-100899 SV_GENERAL xmelab: *E,CUIUCN: Unsupported Verilog interface connection type, when using operator +:
AVSREQ-100857 SV_GENERAL [SV] xmsim crash with an automatic function including a const ref argument
AVSREQ-100834 FUNC_SAFETY_CONCURRENT MESSAGE: rts_abrthandler - SIGABRT unexpected violation pc=0x387c832495 addr=0xa4b2000021fb
AVSREQ-100833 FUNC_SAFETY_CONCURRENT MESSAGE: rts_net_fse - bad stopreason (0)
AVSREQ-100831 LP_1801 ACINVD message is wrong as create_assertion_control command cannot be applied to assertions OUT of a IEEE 1801 scope.
AVSREQ-100806 LP_1801 1801: Issue with reset @ power-up on verilog process
AVSREQ-100793 DMS_ELAB Improve error message CUNDCM
AVSREQ-100785 ELAB_SV protected keyword being ignored in some cases
AVSREQ-100760 DMS_LP_AMS Elaboration fails with "MESSAGE: xst_isprot - default" for AMS test case having wreal SupplySensitivity
AVSREQ-100746 COVERAGE_CODE COVNES extended error message has typo in code example
AVSREQ-100745 COVERAGE_FUNCTIONAL Request ability to deselect assertions via deselect_coverage CCF
AVSREQ-100721 SIM_PERFORMANCE From 19.05-a001 xcelium evaluates 1'hx != 1'hx to 0
AVSREQ-100714 SIMVISION_WAVEFORMS SimVision becomes unresponsive while revoking and deleting a VHDL vector from waveform
AVSREQ-100706 SIM_VCD Voltus unable to read VCD
AVSREQ-100423 ELAB_BIND Config cell clause does not honor library_identifer prior to cell_identifier
AVSREQ-100415 SIMVISION_WAVEFORMS trying to group and ungroup signals with the same group name causes simvision and entire X session to become unresponsiv
AVSREQ-100385 XPROP_GENERAL XPINST messages are not xmbrowse compatible even when VL_XMBV is set to ON in xfile
AVSREQ-100304 SIMVISION_GENERAL Tracing signals causes SimVision*F,INTERR: Internal error (CDS.LIB: (unexpected parse error) %s '%s' on line %d
AVSREQ-100241 ELAB_SV Elaborator fatal internal exception instead of indicating an error.
AVSREQ-100174 ELAB_SV Incisive Internal Exception with parameter of real datatype to $info task
AVSREQ-99983 SV_GENERAL ncelab error CUVDST when connecting using wildcard named port connection
AVSREQ-99946 SV_GENERAL Need struct support with dot-star : CUVDST dot-star did not connect child port
AVSREQ-99421 ESW_ESWDBGEN Indago becomes unresponsive due to unsupported tarmac format
AVSREQ-99412 SV_GENERAL *E CFNOSF - System function calls are not allowed in constant functions
AVSREQ-99405 SIM_SV_VHDL NCMLTY error message is wrong / incomplete
AVSREQ-99403 XRUN_GENERAL xrun can't accept -svperf options as documented
AVSREQ-99392 ELAB_SV xmelab: *E,ARNOTL : Argument to out parameter is not a legal lvalue.
AVSREQ-99390 RAND_GENERAL Constraining a class object with unpacked array in SV based on an unpacked array wire leads to incorrect result
AVSREQ-99379 RAND_SOLVER unexpected constrain solution space change when update VRST_HOME form 19.03.010 to 19.09.002
AVSREQ-99365 DEPRECATE_SIM_GENERAL -xminit_log does not work with -xmhierarchy
AVSREQ-99359 SIM_VHPI Simple Port Sampling Post Update Value when -linedebug is not used
AVSREQ-99358 SIM_VHPI VHDL Optimizations - Delta Cycle - Simulation Fail [-vhdl_seq_nba issue?]
AVSREQ-99351 DMS_SVAMS ncelab encountered an internal exception error
AVSREQ-99337 GLS_SDF Xmelab fatal error with message vst_offset () - invalid class, class 557
AVSREQ-99336 CORE_PARSE_SV Xcelium does not parse default values in extern functions properly
AVSREQ-99330 DMS_LP_AMS *E,DUPGCN error for UDN supply net connection in DMS model that also has a liberty model attached
AVSREQ-99327 DMS_VLOG Support for $test$plusargs statement in a resolution function
AVSREQ-99300 SV_CODEGEN xmelab: *F,CGFAIL: Code generation failed in ixcom compile.
AVSREQ-99298 ELAB_SV unexpected elab error due to hierarchical reference
AVSREQ-99290 FUNC_SAFETY_ELAB Elaboration internal error with MESSAGE: vst_xdecomp_expr - illegal KIND of expression
AVSREQ-99289 GLS_SDF Xcelium internal error at elaboration with message: sv_seghandler - trapno -1 addr(0x30)
AVSREQ-99287 VPI_GENERAL Memory leak on specman interface with SystemVerilog array of wires
AVSREQ-99283 DEPRECATE_SIM_GENERAL Return value of floor is incorrect when using it in verilog-ams (for a wreal model)
AVSREQ-99279 GLS_SDF Elab internal error when using dumptiming
AVSREQ-99273 DMS_LP_AMS L2E_2_LPS connect module fails to fetch right supply level in vPwrArgArray[1] when PD connected to logic is switchable
AVSREQ-99271 DMS_LP_AMS L2E LPS CM at bus port has supply vPwrArgArray[1] from default vsup value rather than from PD of logic side
AVSREQ-99270 DMS_LP_AMS E2L_2_LPS connect module fails to fetch right supply level in vPwrArgArray[1] when PD connected to logic is switchable
AVSREQ-99266 DMS_LP_AMS AMS: Wrong signal conversion in L2E LPS connect module path
AVSREQ-99263 IXCOM xmelab Internal Exception on ixcom generated code, cu_validate_ifc_inst_with_io_ports instance POT absent
AVSREQ-99259 SIMVISION_GENERAL Allow specification of the LWD location on the SimVision command line, as is supported in Indago
AVSREQ-99247 RAND_SOLVER randomization calls failure to reproduce
AVSREQ-99243 SIM_SV_VHDL xmsim: *E,ILLNUM: Expecting a real numeric literal (-inf.0) when using $xm_mirror
AVSREQ-99242 UVM_SV 'uvm_message -stop_on_error' stops test even when errors disabled in UVM 1.2
AVSREQ-99206 LP_CPF Unexpected isolations on block_id[3:0] driven by literals with -boundary_ports on AON
AVSREQ-99205 LP_CPF MESSAGE: pwrIsoMarkPort - dlp src and dst same [testbench.top.ss_adma.tcu.tcu_select[0]]
AVSREQ-99203 SIM_TCL #include "tclPlatDecls.h" in tools/inca/include/xmtcl/tcl.h
AVSREQ-99186 LP_1801 signal in interface not working as expected in low power simulation
AVSREQ-99180 SIMVISION_UVM_VIEWERS enable UVM button even when there is C/C++ code loaded thru DPI/VPI
AVSREQ-99179 SIM_WRITE_METRICS -vsof_dir option failure in multi-step xrun
AVSREQ-99178 DMS_ELAB Invalid SystemVerilog type on mixed-signal connection error on array ports
AVSREQ-99175 XRUN_GENERAL How to prevent xrun invoking ixcom when no hardware related switches being used?
AVSREQ-99174 LP_1801 Fatal elaboration build in XLM19.09.001 for LP RTL in customer project
AVSREQ-99163 DMS_LP_AMS LPS connect module to infer the secondary domain of the isolation rule for its power supply
AVSREQ-99153 COVERAGE_SIMULATION xmsim INTERR sv_seghandler at coverage dump
AVSREQ-99151 SIM_USABILITY SYSTF VISNOSD generated when -nocellaccess used with $countdrivers
AVSREQ-99139 SV_GENERAL SV interface doesn't update the signal without a buffer
AVSREQ-99137 LP_1801 lps_cov fails after Simulator created a bad database for SimVision and Indago
AVSREQ-99135 SIM_SV_VHDL resolution of VHDL signal driven by VHPI in mixed-language design wrong
AVSREQ-99124 DEBUG_SIMCOMPARE isolation missing on an interface connected back2back to an another interface
AVSREQ-99122 VPI_GENERAL xmsim Internal Exception with MESSAGE: sv_seghandler - trapno -1 addr(0xcdbd8)
AVSREQ-99119 VPI_GENERAL event_port on logic array triggers wrong events
AVSREQ-99117 LP_1801 xmelab: *F,NACTSCP: [LPS] even when no upf specific commands in file
AVSREQ-99115 LP_1801 xmelab performance with UPF VHDL
AVSREQ-99105 DMS_ELAB ncelab Internal Exception when setting -setd with module name having 256 characters
AVSREQ-99103 ELAB_BIND New command line option to only see warnings from libverbose
AVSREQ-99097 SYSC_KERNEL sc_vector_assembly operator = lacks return statement
AVSREQ-99095 SV_GENERAL xmvlog: *E: System function calls are not allowed in constant functions [10.3.5(IEEE)].
AVSREQ-99093 SV_GENERAL Structure containing enum type is not initialized by default assignment pattern
AVSREQ-99086 RAND_SOLVER RNDTRATF/RNDCNSTE: A reference to a rand variable in an array index is not currently supported
AVSREQ-99080 SIM_TCL Setting line breakpoint on MSIE snapshot causes the simulator to use excess memory and exit with an SVMLEX error
AVSREQ-99073 DMS_AXUM Internal exception in hierarchical dynamic voltage supply flow in conjunction with cellupport in ie card
AVSREQ-99071 GLS_SDF GLS : xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-99067 LP_CPF negative delay compensation is different with and without lps_dbc
AVSREQ-99056 XRUN_GENERAL Option to disable ixcom queries
AVSREQ-99046 XRUN_GENERAL PRENOP: Couldn't open file xrun.hrd when no write permission
AVSREQ-99033 MSIE_ELAB Observed xmelab: *E,RNGDIR error within protected source code error in auto MSIE flow. Whereas monolithic is fine.
AVSREQ-99028 SIM_SV Xmsim:INTERR: INTERNAL EXCEPTION issue in xcelium version 19.03
AVSREQ-99022 DEPRECATED_CORE_PROFILER UVM ML with Enet XT and xprof internal error
AVSREQ-98994 SV_GENERAL clog2 error when used in a function
AVSREQ-98988 SV_GENERAL *E,CICAPC incompatible or unsupported array port connection.
AVSREQ-98983 SIMVISION_CONSOLE text search in simvision console doesn't work properly when line wrap using uvm_info
AVSREQ-98943 DMS_LP_AMS L2E_LPS CM gives default value of 1.8V and ignores the power supply coming from the power domain
AVSREQ-98932 SIMVISION_DESIGN_BROWSER Design File Search does not work
AVSREQ-98927 CORE_PARSE_SV xmelab internal exception error with - odpfunc unknown wad struct id 'ifs_vst'
AVSREQ-98919 LP_1801 lps_cov doesn't generate all the defined coverage on power states
AVSREQ-98917 VHDL_PARSE Unexpected Signature mismatch error with Alias definition
AVSREQ-98816 XRUN_GENERAL xrun process becomes unresponsive with NC jobs dispatcher on infinite loop of system calls
AVSREQ-98814 ELAB_BIND LWD compilation failure "xmelab: *E,MULVLG" when using Verilog configuration file
AVSREQ-98812 ELAB_SV different behavior between Xcelium standalone and other tools for the error xmelab: *E,CUIOAI
AVSREQ-98810 MSIE_SIMULATION MSIE fail on dynamic cast
AVSREQ-98777 DEPRECATE_SIM_GENERAL force injected by Metastability is not released on the signal
AVSREQ-98762 SV_CODEGEN INFRA-501 elaboration fails in 19.08 with code generation errors
AVSREQ-98753 GLS_GENERAL Add support for *E,SBPDR: Unsupported connection for a register driven path delay in specify block
AVSREQ-98740 GLS_GENERAL DOC: SDF Timing Annotation, WIDTH keyword clarification needed
AVSREQ-98573 SV_GENERAL issue around Non-blocking assignments
AVSREQ-98561 CORE_PARSE_SV AMSD simulation causing Internal Exception error MESSAGE: stderror - no noninvisible source
AVSREQ-98557 DMS_LP_AMS Avoid the need for mandatory nominal condition for -lps_ams_lsr to insert level shifter rule
AVSREQ-98515 SV_CODEGEN xmvlog_cg INTERR: gq_ttom - got a pointer
AVSREQ-98509 XRUN_GENERAL CLONE can't use specman seed for lps_enum_rand
AVSREQ-98506 XRUN_GENERAL can't use specman seed for lps_enum_rand
AVSREQ-98410 SIM_TCL Setting line breakpoint causes the simulator to use excess memory and exit with an SVMLEX error
AVSREQ-98347 VHDL_PARSE unclear error ncvhdl_p: *E,APNPFX : can not make sense of P
AVSREQ-98264 SIM_VCD $dumpvars dumping the packed array in incorrect form in VCD
AVSREQ-97617 SIM_SV Warn user if loading shared object that defines a routine with the same name as a routine already in ncsim
AVSREQ-97472 DMS_AXUM Support multi-dimensional array or vectors to electrical ports
AVSREQ-97347 DMS_AXUM Support multi-dimensional array or vectors to electrical ports
AVSREQ-97212 COVERAGE_GENERAL Error in option for select_functional in ccf file is not flagged by elaborator
AVSREQ-97165 SV_GENERAL Need support for clog2 system task in function used in localparam
AVSREQ-97026 DEPRECATE_CORE_AMSD Add switch to honor VAMS file name extension when -sv switch supplied
AVSREQ-96948 CORE_PARSE_SV protected file causes internal error : ifungetc - EOF pushback
AVSREQ-96932 COVERAGE_MERGING Request ability to merge when module names are different but content is the same
AVSREQ-96756 ASSERTION_SVA $assertoff is not working inside generate block/for loop
AVSREQ-96716 SIM_VHPI VHDL event_port Sensitivity
AVSREQ-96542 SV_GENERAL CFNOSF error when calling $clog2 from constant function
AVSREQ-96487 SIMVISION_GENERAL Simvision trace color change is inconsistent with the preview icon
AVSREQ-96480 ELAB_VHDL Simulator not erroring RTL errored by Synthesis for negative vector range
AVSREQ-96433 LP_1801 Support for apply_power_model -port_map to a constant
AVSREQ-96371 DMS_SIM Add ability to dynamically swap pointer to UDR (nettype resolution function)
AVSREQ-96350 CORE_PARSE_SV bind on array of instances gives *E,ILLBPS error, works if used with the hierarchical path
AVSREQ-96071 SIMVISION_SCHEMATIC Schematic tracer is frozen when trying to trace back modports used as module ports.
AVSREQ-95894 ASSERTION_SVA hierarchical reference support in assertcontrol system tasks
AVSREQ-95687 LP_CPF Signal value not following the driver in LP-MS simulation
AVSREQ-95673 LP_1801 report if the netlist is modified due to UPF is not matching SDF netlist
AVSREQ-95670 LP_1801 interconnect SDF annotation will be ignored in UPF conext
AVSREQ-95516 ASSERTION_COMPILE Request ACTBDN warning to be generated during ncelab
AVSREQ-95321 DMS_AXUM Support SystemVerilog multi-dimensional generate statements and arrayed vectors(MDAs) in AMS.
AVSREQ-95284 DMS_AXUM AMS simulator to support connections of multi-dimensional arrays or vectors to electrical ports
AVSREQ-95076 DEBUG_PROBE Request to change ncsim error DBOBBD to warning message
AVSREQ-95045 XRUN_GENERAL Please add the options xmls_all xmls_dep xmls_so xmls_ss to the xrun documentation
AVSREQ-95043 ELAB_BIND -name option is not obeyed when verilog configuration is set as Top
AVSREQ-95038 DMS_AXUM Support connection of multi-dimensional array or vector to electrical port
AVSREQ-95029 DEBUG_PROBE Request ability to downgrade TCL probe error(ncsim: *E,DBOBBD) to warning(/soft error) using -xmwarn option
AVSREQ-94875 SPECMAN_E GC internal error when opening Indago gui post process
AVSREQ-94848 SIM_RND_DEV_CODE xmsim sv_seghandler WIRE 4 inputs 19.10a1
AVSREQ-94830 DMS_ELAB Discipline resolution process fails in a simple MS simulation
AVSREQ-94808 SV_PERFORMANCE Tool failure on simulation when elaborating with UPF
AVSREQ-94753 CORE_PARSE_SV APNMBR - Getting wrong error in type parametrized virtual class
AVSREQ-94734 LP_1801 Internal exception with 19.07.e353: MESSAGE: pwrVlogDisableShutOff - object to signal error
AVSREQ-94710 LP_CPF Power source should drive the domain and power modes should be ignored without a *E,PSILLPM: [LPS] error
AVSREQ-94705 RAND_SOLVER TRAT: Enhancement: A reference to a rand variable in an array index for array of handles
AVSREQ-94666 RAND_GENERAL Seed mismatch from library name with -xceligen ignore_worklib_name
AVSREQ-94653 SIMVISION_DB_UTIL AMSD: simvisdbutil strips off the units information
AVSREQ-94651 RAND_SOLVER randomize failed in inline constraint due to wrong enum value selection with -xceligen on=1903
AVSREQ-94650 RAND_SOLVER array.sum with int casting(LRM recommended) shows RNDXZW with -xceligen on=1903
AVSREQ-94639 VPI_GENERAL xmsim error for unused vpi or system task
AVSREQ-94629 SV_CODEGEN xmelab: *F, CGFAIL: Code generation failed for one or more modules.
AVSREQ-94628 RAND_SOLVER Foreach constraints with function calls does not generate expected randomized values
AVSREQ-94622 LP_1801 logic_expr_drives_supply_expr : VDD signal has 'bx at sequence event time of power up.
AVSREQ-94614 RAND_SOLVER sv randomization does not support sum() operator in multi-dimensional array - works in vcs
AVSREQ-94129 DEPRECATE_CORE_LP 2199222 CCR Unexpected NOCNINP for pg_pins of PA cells
AVSREQ-93578 SV_GENERAL elaboration internal error with upgrade to xcelium 19.03.004
AVSREQ-93524 SV_GENERAL Getting CFNOSF Error for using $clog2 in parameter function value
AVSREQ-93523 SV_GENERAL Add support for using alias with hierarchical reference
AVSREQ-93511 DEPRECATE_SIM_GENERAL ASNUSE error when a field in a packed struct is forced
AVSREQ-93508 DEPRECATE_SIM_GENERAL xmvlog error for force on packed struct members - xmvlog: *E,ASNUSE
AVSREQ-93506 LP_1801 no isolation on SV interface that marked on lps.log as isolated
AVSREQ-93449 SV_GENERAL *E, NAEXERR : Illegal expression in net alias statement hierarchical reference
AVSREQ-93448 SV_GENERAL *E,NOTPAR, xmvlog does not support variable multiplier in multiconcats
AVSREQ-93446 SV_DPI error when importing DPI-C system function
AVSREQ-93409 SV_DPI DPI_COMPATIBILITY_VERSION flag in uvm_dpi.h is both unnecessary and wrong
AVSREQ-93395 DEPRECATE_SIM_GENERAL force a packed struct field errors out
AVSREQ-93382 SV_CODEGEN elaboration internal error at xmvlog_cg with gq_vload_defval_fill
AVSREQ-93381 SV_GENERAL not support to use variable in the front of {}
AVSREQ-93380 SV_GENERAL xmelab: *E,NAEXERR: Illegal expression in net alias statement - hierarchical reference
AVSREQ-93370 SV_GENERAL hierarchical reference of signals in alias statement
AVSREQ-93336 SV_GENERAL xmelab: *E, NAEXERR : Illegal expression in net alias statement hierarchical reference
AVSREQ-93327 SV_CODEGEN xmvlog_cg internal exception with MESSAE: gc_lea -src ireg
AVSREQ-93326 DEPRECATE_SIM_GENERAL ASNUSE error when forcing member inside packed struct
AVSREQ-93281 SV_GENERAL System function calls failure using IUS
AVSREQ-93274 SIM_PERFORMANCE Running intointernal error MESSAGE: sv_seghandler
AVSREQ-93273 RAND_DEBUG Running into internal error with -xceligen tc_fail MESSAGE: Unexpected SIGILL from native code
AVSREQ-93247 RAND_SOLVER xmsim: *E,RNDCNSTE reference to a rand variable in an array index
AVSREQ-93145 MSIE_ELAB xmelab: *E,CUVUNF (./msie.sv,50|128): Hierarchical name component lookup failed at 'sprint'.
AVSREQ-93143 MSIE_ELAB xmelab: *E,CUVUNF (./testcase.sv,17|74): Hierarchical name component lookup failed at 'MY_REG'
AVSREQ-93103 ELAB_SV SOXNBA error - streaming concatenation on LHS with non-blocking assignment
AVSREQ-93095 ELAB_SV $bits does not provide correct values in inteface instance parameter and accessed through a modport
AVSREQ-93093 RAND_SOLVER sv randomization does not support sum() operator in multi-dimensional array - works in vcs
AVSREQ-93089 DEPRECATE_SIM_GENERAL ASNUSE error forcing object
AVSREQ-93085 SIM_SV $value$plusrags("gp_address=%h", gp_address) gives format error with underscore +gp_address=800_400
AVSREQ-93081 VHDL_GENERAL -relax does not work in combination with -linedebug or -access +rwc
AVSREQ-93072 MSIE_SIMULATION tool failure during simulation with MSIE only
AVSREQ-93050 DEPRECATE_SIM_GENERAL Support force on members of a packed struct
AVSREQ-92738 DMS_ELAB xrun errors out with error SFE-23
AVSREQ-92637 MSIE_ELAB AMSIE - force from incr to prim not moving outside of prim boundary
AVSREQ-92634 ASSERTION_SVA Using $past in the connectivity of a property instantiation causes a crash or E,DUPIDN error
AVSREQ-92627 COVERAGE_FUNCTIONAL coverage model has the low level modules at the top outside the top level TB hierarchy
AVSREQ-92593 LP_1801 *E,NOISELE - isolation rule has been optimized away without -lps_iso_hybrid
AVSREQ-92569 DEPRECATED_CORE_XPROP support for XPUBR or UNSXPC: Break statement in if block
AVSREQ-92565 DEPRECATED_CORE_XPROP Support for xprop_off attribute on begin block
AVSREQ-92551 DEPRECATED_CORE_PROFILER mem_prof xprof Internal Exception error
AVSREQ-92543 DEPRECATED_CORE_XPROP Signal is not driven correctly when using xprop C with enable_opt_var_core (JIRA-3175)
AVSREQ-92540 MSIE_ELAB Internal error on genherf with -msieunlock reg_prune_optm and -enable_pes_woomr
AVSREQ-92539 LP_1801 always@(*) block doesn't get evaluated at power up
AVSREQ-92536 ELAB_SV Unexpected ENUMERR with type parameter
AVSREQ-92528 DEPRECATED_CORE_XPROP always_ff incorrect with x-prop CAT mode enabled
AVSREQ-92505 COVERAGE_FUNCTIONAL Warning for hitting ignore_bins
AVSREQ-92489 COVERAGE_FUNCTIONAL Required option to remove instrumentation for cover and assert properties
AVSREQ-92484 LP_1801 automatic always on connection for std cells that are in the testbench scope
AVSREQ-92457 ELAB_SV xmelab: *W,CUVIHR This virtual interface declaration type 'intf' makes hierarchical reference t
AVSREQ-92449 GLS_GENERAL Constant delay (#1) - has one wrong delay during simulation
AVSREQ-92428 LP_1801 Need more informative message instead of generic NOISELE
AVSREQ-92396 ELAB_BIND xmvlog compile error during elaboration - why compile?
AVSREQ-92394 LP_1801 create a command line option that includes commonly recommended options
AVSREQ-92310 DEPRECATED_CORE_XPROP support for xprop XPUCS or UNSXPC: Continue statement in if block
AVSREQ-92309 DEPRECATED_CORE_XPROP support for XPIMT or INVXPC: Class function or method call in block
AVSREQ-92204 MSIE_ELAB Force/assign not propogated when having nested primaries and the "top" is a primary
AVSREQ-92189 SIM_PERFORMANCE simulation behaves incorrectly once we turn off VTW and probe signals to waveform
AVSREQ-92091 LP_1801 create an error when there is a liberty model instantiated within a PA model (outer PA has no liberty)
AVSREQ-91962 RAND_SOLVER terminate called: mbi::ImproperInputError pieces.size() == 0 PwFunction::get_range()
AVSREQ-91958 XRUN_GENERAL Bad command passed to -prefix_ncsim results in cryptic failure
AVSREQ-91956 ELAB_BIND Unexpected CUVIHR from target of interface bind
AVSREQ-91949 LP_1801 elab time from 4 hours to 20 hours with upf -testbench
AVSREQ-91947 SIM_PERFORMANCE INTERR xmvlog_cg in gq_e_dpi_function
AVSREQ-91943 SIM_SV Clocking block missing signal with input skews (non-zero skew becomes zero due to timescale)
AVSREQ-91939 GLS_GENERAL Functional mismatch from -nolog and CentOS-6.9
AVSREQ-91834 LP_1801 *E,UDPTST with add_power_states with && and create_pst
AVSREQ-91821 LP_1801 Array limit supported by RTL is not supported by LP
AVSREQ-91785 RAND_SOLVER Simulation stuck at randomization in mbi::Generator::RPs from librnc.so
AVSREQ-91722 ELAB_BIND GLS Parallel build is utilizing ~80% time in Genhref stage
AVSREQ-91716 ELAB_SV Elaboration performance is suffering due to "after instantiating" bucket
AVSREQ-91694 XPROP_GENERAL unsupported xprop multiple drivers
AVSREQ-91405 CORE_PARSE_SV Unexpected DEFFIN in assert final
AVSREQ-91404 CORE_PARSE_SV EXPEND message does not give enough information to debug
AVSREQ-91356 SIM_SV Runtime fatal BSSXCD doesn't give enough debug information
AVSREQ-91201 ASSERTION_SVA $assertkill does not work when index is genvar. Explicit indexing works
AVSREQ-90943 LP_1801 nested curly braces around supply handle leads to UDFUOBJ
AVSREQ-90750 ELAB_SV Invalid CONOTR with specific struct in clocking block
AVSREQ-90645 ASSERTION_SVA $assertoff arguments should be checked at elab time
AVSREQ-90550 DEPRECATED_CORE_XPROP Internal error when using xprop with VHDL
AVSREQ-90544 GLS_PERFORMANCE "-enctran" option makes Internal Error.
AVSREQ-90542 DMS_ELAB xrun fatal error when expand bus bit for pure digital case with SV-UDT and real number modeling
AVSREQ-90541 SIM_TCL internal error for Tcl execution
AVSREQ-90540 LP_1801 2die save & restore signal seems to be not o.k. in lps.log
AVSREQ-90539 DEPRECATED_CORE_XPROP Enable new xprop/RTL optimizations under -newperf
AVSREQ-90538 LP_1801 Enable new LP optimizations under -newperf
AVSREQ-90536 VPI_GENERAL xmsim error for unused vpi specified in afile
AVSREQ-90533 LP_1801 find_object -transitive true doesn't work in the terminal boundary
AVSREQ-90532 LP_1801 INTERR during LPX build LWD database generation
AVSREQ-90526 GLS_TIMING "-entrandelay" doesn't make the specify iopath delay show in the timing
AVSREQ-90524 SV_DPI ERROR : Object found for name <> but language domain is not supported !!! Works in earlier versions.
AVSREQ-90522 PROFILER_XPROF xmsim INTERR at the end of RTL simulation with -xprof
AVSREQ-90497 ELAB_SV XMELAB: *F,INTERR MESSAGE tl_rwait_disqualify - DYNWAIT not set
AVSREQ-90496 ELAB_SV Elaboration times degrades by 8 minutes while using the option -enable_rswt.
AVSREQ-90495 SIM_USABILITY sscanf not returning proper floating point precision.
AVSREQ-90492 GLS_TIMING "-entrandelay" makes an internal error during xmvlog_cg
AVSREQ-90490 GLS_GENERAL xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-90487 GLS_TIMING Timing Violation is reported only 64bit mode
AVSREQ-90486 LP_1801 Supply net connections inferred by apply_power_model -supply_map, are not driving VDD/VSS pins in model
AVSREQ-90485 SV_CODEGEN xmvlog_cg:*F,INTERR MESSAGE: via_get_ots_field: field 1 is invalid for VST_D_REF_ARG
AVSREQ-90481 MSIE_ELAB single xrun MSIE flow with multiple primary should give error when non compiled SDF file is provided in sdf command file
AVSREQ-90480 CORE_PARSE_SV Preprocessor adds space to parameter breaking escaped names
AVSREQ-90474 RAND_SOLVER TRAT Fail Over : Complex function mref chain in function call
AVSREQ-90470 LP_CPF Wrong clock violation reported for clk_low_strict retention model which is a deviation to spec
AVSREQ-90467 RAND_SOLVER xmsim: *E, RNDCNSTE due to "Solve before not allowed on empty array"
AVSREQ-90466 GLS_SDF Internal simulation tool failure
AVSREQ-90465 GLS_TIMING The binded instance input port has different timing than what is instantiated directly
AVSREQ-90464 DEBUG_SIMCOMPARE SimVision becomes unresponsive at post processing on LSF (while opening design in source browser)
AVSREQ-90463 SV_CLASSES MIMPST error when defining a class with the same name as an imported package class
AVSREQ-90462 DMS_ELAB AVSREQ-72448 ELAB PERF: ADI memory usage optimizations for -RNM_NO_CM_OR_VAMS_WREAL feature integration CCR
AVSREQ-90460 XRUN_GENERAL multiple definition/first defined here from functions defined in .a archive
AVSREQ-90459 SV_CODEGEN INTERNAL EXCEPTION: gc_lea -src ireg
AVSREQ-90458 XRUN_GENERAL SystemC support warning is suppressed by -gcc_vers.
AVSREQ-90457 LP_1801 Elaboration slowdown seen in cu_optimize in 19.09.v001
AVSREQ-90456 ELAB_SV xmelab INTERR vst_class() - null ptr
AVSREQ-90455 CORE_PARSE_SV xmvlog internal error due to p3_mexpr_depth - default VST_E_METHOD_FUNCTION_CALL
AVSREQ-90451 MSIE_ELAB Provide debug option to force manual href permission in single step MSIE flow
AVSREQ-90448 MSIE_ELAB -primtop/-replicated_top and -replication_metrics used together gives errors DYNNPM STIMSP
AVSREQ-90444 DEBUG_PROBE DLDDRD Fatal error when using -memopt and shm dumping to cells
AVSREQ-90443 DEPRECATED_CORE_XPROP always_ff inside for generate causing runtime slowness resulting in timeouts
AVSREQ-90440 GLS_GENERAL The difference in behavior between Incisive and Xcelium
AVSREQ-90435 CORE_PARSE_SV Chamber V12 testcase started giving parser error PMBDVME on nightly AGILE
AVSREQ-90414 DMS_ELAB Improve error message xmelab: *F,AMSNOPD: -allowsim option is not allowed in AMS designs
AVSREQ-90413 FUNC_SAFETY_SIM xfr reports wrong annotation with virtual strobe only and UU
AVSREQ-90410 DMS_LP_AMS xmelab Internal Exception using IE model when one port floating
AVSREQ-90407 MSIE_ELAB MSIE Elaboration internal error
AVSREQ-90406 VHDL_GENERAL -relax only fixed ncvhdl_p, not ncvhdl_cg
AVSREQ-90405 SV_CODEGEN Elaboration internal error : gq_xflink - q_s1 not marked as pointer (nightly agile)
AVSREQ-90404 COVERAGE_CODE vlog_short_circuit causes spurious hole to appear
AVSREQ-90402 DEPRECATE_SIM_GENERAL add check for source marker consideration in stream crc calculation ...
AVSREQ-90399 ASSERTION_SIM xmsim: *W,ACTBDN (<...>): Invalid assertion or scope name argument to $assertoff assertion co
AVSREQ-90397 DMS_MSIE MSIE+RNM: concatenation of wreals as hiconn to array of wreals in loconn generates CUVIRP error
AVSREQ-90396 RAND_SOLVER xmsim: *F,RNDUNR XCELIGEN assertion failed - ! sc_list.empty()
AVSREQ-90392 DEPRECATED_CORE_XPROP Internal : sv_seghandler - trapno-1 addr((nil))
AVSREQ-90390 SIM_SV_VHDL INTERR during compilation with 19.08agile . 1809 works.
AVSREQ-90388 RAND_SOLVER Xceligen internal assertion XCELIGEN assertion failed - !! _const_value
AVSREQ-90384 DEPRECATED_CORE_PROFILER INTERR during xprof run
AVSREQ-90380 DEPRECATE_SIM_GENERAL sensitivity list based always block is not pruned.
AVSREQ-90373 LP_1801 SV interface could not add isolation when the interface is passed from child instance.
AVSREQ-90370 RAND_DEBUG Running into internal error with -xceligen tc_fail MESSAGE: sv_seghandler
AVSREQ-90368 DMS_ELAB AMS elab gives *E, CUNSVP error, when a packed struct array element is NOT connected to electrical
AVSREQ-90366 DMS_LP_AMS CPF elab internal error when processing bidirectional SVRNM model - using named ports with one of the port floating
AVSREQ-90365 GLS_GENERAL SDF annotation issue
AVSREQ-90363 DEPRECATE_ELAB_GENERAL INTERNAL: sv_seghandler - trapno -1 addr(0xfffffffffcc80f90)
AVSREQ-90359 SV_CODEGEN xmvlog_cg gq_igen - OP_STORE s1 is SVHR
AVSREQ-90358 ELAB_SV xrun: -gpg 'AA =>' ; the parameter AA here has to be case-sensitive for Verilog language
AVSREQ-90357 SIM_TCL Same tcl code evaluates to an incorrect value in newer Xcelum 19.08 builds compared to old Xcelium 18.08 build
AVSREQ-90348 SIM_TCL TCL version change in Xcelium 19.03.xxx causing customer test case to fail
AVSREQ-90347 ELAB_SV SystemVerilog instance parameter values do not override parameter default values
AVSREQ-90334 LP_1801 Force in initial block not working properly
AVSREQ-90333 ELAB_SV INTERNAL ERROR: vst_offset () - invalid class, class 895
AVSREQ-90329 MSIE_ELAB Elaboration becomes unresponsive after "Loading native compile code ... Done"
AVSREQ-90328 SIM_SV Forced output value does not propagate to connected wire
AVSREQ-90321 FUNC_SAFETY_SIM Unexpected results while running the fault run in serial and concurrent mode
AVSREQ-90320 DEPRECATE_ELAB_GENERAL BNDWRN warning generated in customer design
AVSREQ-90311 LP_1801 PF nwell don't connect to power when power was updated to explicit supply net.
AVSREQ-90309 COVERAGE_FUNCTIONAL xmvlog: *E, ECRIEX (test.sv,19|9): Illegal expression within cross declaration
AVSREQ-90302 ELAB_SV "Getting the width of an interface signal with the $bits function sometimes returns the wrong result."
AVSREQ-90286 FUNC_SAFETY_FAULT_DB Unexpected results reported by xfr utility while running the fault simulation in serial mode
AVSREQ-90283 SIM_SV clocking block output delay not driven correctly with 1ps
AVSREQ-90273 VPI_GENERAL HALSIG causes internal error in linting tool
AVSREQ-90265 SIMVISION_DB_UTIL packed dimension issue with vcd conversion
AVSREQ-90252 COVERAGE_GENERAL add standard merge support for merging named types from formal when 'set_code_fine_grained_merging' is set in sim db
AVSREQ-90233 CORE_PARSE_SV instance with assertion coverage marked as n/a
AVSREQ-90222 LP_1801 the "*" may affect with the detecting "*E,ILLPRT" message for invalid instance path with connect_supply_net
AVSREQ-90218 GLS_SDF Random simulation mismatch in Xcelium ATPG SDF/ZDEL simulation
AVSREQ-90212 GLS_GENERAL INTERR: rts_abrthandler - SIGABRT unexpected violation
AVSREQ-90169 SV_GENERAL Elab improper exit, sv_seghandler - trapno -1 addr((nil)), unable to decompile type 912
AVSREQ-90161 SV_DPI DPI deprecation warning unclear
AVSREQ-90156 LP_1801 simstate is not going to CORRUPT state in add_power_state -update
AVSREQ-90137 LP_1801 no reason to have this as error - *E,NOLPRF: [LPS] -lps_profile is only supported for 1801 LPS.
AVSREQ-90136 SV_DPI DPI NOLWSV in aarch64
AVSREQ-90064 XRUN_UVM -sv_lib <.tool install...>/uvmdpi.so is not getting added to the xmsim.args in 19.03.xxx
AVSREQ-90025 VPI_GENERAL concatenation of mixed reg and wire is not being dumped in FSDB format with VTW
AVSREQ-89929 SIM_USABILITY option nocellaccess could not work with $countdrivers
AVSREQ-89911 LP_1801 Xelium is not processing exclude_elements properly on create_power_domain.
AVSREQ-89748 CORE_PARSE_SV INT_LKFC: xmvlog: *E,EXPIDN (xc_work/v/1n.sv,18|17): expecting an identifier [3.2][3.8][3.9(IEEE)].
AVSREQ-89701 DEPRECATE_ELAB_GENERAL Internal Exception when using twice the switch -enable_reg_vector_fanout in xrun command line
AVSREQ-89699 DMS_AXUM SV-SPICE: unpacked wire with packed bits connected to spice port gives elaboration error BNDERC
AVSREQ-89689 ELAB_SV xmelab: *E,SOXNBA
AVSREQ-89634 DEPRECATE_ELAB_GENERAL Enhancement req.xmelab: *E,STRNOT : Passing string variable to this system task/function is currently not supported.
AVSREQ-89626 CORE_PARSE_SV xmvlog internal error - unexpected signal #11, program terminated (null)
AVSREQ-89608 GLS_SDF Enhancement request regarding "-sdf_ignore_retain"
AVSREQ-89595 MSIE_ELAB MSIE: performance degradation is way more than 15%
AVSREQ-89590 LP_1801 LP domain corruption cancels SDF delay
AVSREQ-89576 MSIE_SIMULATION internal error with line debug only
AVSREQ-89560 SIMVISION_WAVEFORMS LWD with simvision gives multiple database reload dialog box
AVSREQ-89559 DEBUG_SIMCOMPARE SV interface isolation is not consistent between logfile and SimVision tools
AVSREQ-89554 SV_GENERAL Need support for clog2 system task in function used in localparam
AVSREQ-89546 VHDL_GENERAL Add support for OTHERS => '0' for part selects and record elements
AVSREQ-89521 MSIE_ELAB irun -R does not work without -primname options, requires -sv_lib option to work around
AVSREQ-89488 SIM_SV Different parsing for %d in $sscanf and $value$plusargs
AVSREQ-89481 LP_1801 LBRTDM failure related to bus pin that the tool is not able to correlate between liberty and verilog
AVSREQ-89480 XPROP_GENERAL Segmentation fault from NBA
AVSREQ-89479 SV_GENERAL *E, NOTPAR, support for memory_array = {{size}{1'b0}} ;
AVSREQ-89477 GLS_SDF Enhance xcelium annotator to select minumum or maximum delays in SDF when multiple conditions match
AVSREQ-89475 CORE_PARSE_SV xmvlog: *E, NODEFA issue
AVSREQ-89474 DEPRECATE_SIM_GENERAL ASNUSE - Enhancement : force on part select of a packed struct
AVSREQ-89459 DEPRECATE_CORE_LP Unexpected NOCNINP for pg_pins of PA cells
AVSREQ-89447 CORE_PARSE_SV xmvlog Internal Exception: smi_set_sm - object is only a SMI_1ST class yet sel == 1 with coverage
AVSREQ-89433 SV_PERFORMANCE rand_mode is required to be made inlined for simple types
AVSREQ-89419 SV_GENERAL OOMR in alias not supported
AVSREQ-89412 ELAB_BIND AMSUNL: 19.11.a001 cannot resolve library when verilog config has no library binding, works fine in 19.11 Green
AVSREQ-89408 PROFILER_SIM_RUNTIME xmsim INTERR during LPX simulation with -xprof
AVSREQ-89406 RAND_SOLVER Function evaluates incorrectly as a part of constraint
AVSREQ-89375 DMS_LP_AMS LP RTL build time is considerably higher than non LP RTL build time around (4-5X)
AVSREQ-89373 DMS_ELAB huge memory overhead for RTL elaboration (VHDL + mixed signal invovled)
AVSREQ-89307 CORE_PARSE_SV Preprocessor leaves `` in escaped name if immediately follows \ escape
AVSREQ-89219 SIM_USABILITY growing slowdown due to vpi_remove_cb in customer tc
AVSREQ-89096 LP_1801 Simulator created a bad database for SimVision and Indago
AVSREQ-89025 ELAB_SV xmelab: *E,SOXNBA followed by internal error
AVSREQ-89002 MSIE_ELAB MSIE build fails xmelab: *E,CUVSCE (./fcd.sv,15|25): Scoped name component 'my_tag_t' lookup failed at 'foo_addr_base'.
AVSREQ-88970 COVERAGE_CODE Strange SOP coverage tables
AVSREQ-88675 CORE_PARSE_SV SVNOTY, EANASI, MISEXX when using escaped names with `` in macros
AVSREQ-88664 ELAB_SV Support for $bits(hierarchical interface)
AVSREQ-87832 SV_PERFORMANCE New option that will disable access only for clocking block elements
AVSREQ-86958 RAND_SOLVER TRAT: Enhancement: A reference to a rand variable in an array index for array of handles
AVSREQ-86869 COVERAGE_FUNCTIONAL Selectively enabling the sv_mda for toggle coverage to minimize the performance hit
AVSREQ-85981 FUNC_SAFETY Safety client silently dropping faults of type -SA0 or -SA1
AVSREQ-81378 ASSERTION_COMPILE NCELAB tool failure with sv_seghandler - trapno -1 addr((nil))
AVSREQ-79282 MSIE_ELAB Invalid "ncelab: *E,CUVUNF" generated while creating primary partition
AVSREQ-76407 CORE_SV_IN INTERR in anonymous continuous assignment
AVSREQ-76319 RAND_SOLVER Internal exception with message rts_abrthandler
AVSREQ-76295 SIM_PERFORMANCE Deliver 1.4x speed-up to customer using Xcelium 19.12 EHF
AVSREQ-76263 JUPITER_GLST Jupiter: Sim mismatch in SDF sim
AVSREQ-76217 GLS_SDF CCMPR02199053 CCR Enhance xcelium annotator to select minumum or maximum delays in SDF when multiple conditions match
AVSREQ-75874 DMS_MSIE MSIE elaboration internal exception with primary and incremental set up
AVSREQ-75857 LP_1801 2191821 CCR 2tops save & restore signal seems to be not o.k. in lps.log
AVSREQ-75816 FUNC_SAFETY_SIM Fault is reported as undetected if the signal changes passes a SystemC code
AVSREQ-75794 DEPRECATE_CORE_AMSD Integration CCR for HONORVAMS
AVSREQ-75539 GLS_GENERAL DOC: "-simport" is not supported with registers.
AVSREQ-75512 JUPITER_ENGINE Affinity setup is wrong
AVSREQ-75442 MSIE_ELAB Improve partitioner signature algorithm to include defparams
AVSREQ-75441 MSIE_ELAB Automate the replicated_top flow
AVSREQ-75438 LP_1801 xmelab does not complete, when it accept UPF.
AVSREQ-75241 LP_1801 Elaboration runs 5x slower with -lwdgen
AVSREQ-75055 MULTI_CORE_FRONT_END non-constant loop condition needs to be auto-classified and not ERROR out
AVSREQ-74972 LP_1801 R&D: fixing CCMPR02188706 in Agile
AVSREQ-74968 MULTI_CORE_COMPILER request to support some styles of immediate and nested assertions
AVSREQ-74949 JUPITER_ENGINE Jupiter South failure
AVSREQ-74838 CORE_SV_US source_debug flag add too much info to compilation log file
AVSREQ-74798 VPI_GENERAL 2189955 CCR xmsim error for unused vpi specified in afile
AVSREQ-74721 MULTI_CORE_COMPILER pull $display, delay and $finish out of always block to reduce egress
AVSREQ-74580 CORE_RAND Randomization has encountered a bug
AVSREQ-74574 MULTI_CORE_COMPILER break non-constant initialization in a function into two lines so it can be ACC-ed
AVSREQ-74573 MULTI_CORE_COMPILER support functions imported in a module from packages
AVSREQ-74244 MSIE_ELAB Partitioner signature mechanism for AutoIMC/Replicated top
AVSREQ-74120 LP_1801 make SVUNSUS a soft error when unpacked structs are supported in December release
AVSREQ-74075 LP_1801 unique message for unpacked unions when encountered in a domain in low power
AVSREQ-73864 LP_1801 the following messages need to be changed to soft error
AVSREQ-73861 MULTI_CORE_COMPILER structure getting updated when it should not
AVSREQ-73726 MULTI_CORE_COMPILER element of structure not getting updated in MC
AVSREQ-73639 LP_1801 create unique message when isolation is being attempted on a floating input port
AVSREQ-73534 MULTI_CORE_COMPILER removing buffers stage taking a long time in debug flow
AVSREQ-73354 JUPITER_GLST Jupiter: sim mismatch against Single Core in PATPG GLST
AVSREQ-73211 CORE_SV_IN simulation does not stop on conditional breakpoint, although condition is met
AVSREQ-73191 MULTI_CORE_GLST MC GLST Timingcheck violation does not match SC result
AVSREQ-73092 JUPITER_ENGINE Jupiter simulation internal error at beginning of simulation
AVSREQ-73068 JUPITER_ENGINE Jupiter Codegen internal exception
AVSREQ-72840 CORE_PARSE_SV 2067458 CCR protected file causes internal error : ifungetc - EOF pushback
AVSREQ-72837 CORE_PARSE_SV 2167985 CCR Crash in xmvlog due to p3_mexpr_depth - default VST_E_METHOD_FUNCTION_CALL
AVSREQ-72762 MULTI_CORE_FRONT_END module name created in ske.sv is illegal and causes ske compilation failure
AVSREQ-72726 MSIE_PERFORMANCE Fliter Cloned and Parameterized snapshots in Auto-MSIE Partitioner
AVSREQ-72496 DMS_MSIE -replicated_top + SVWreal: Internal error when doing final stitch
AVSREQ-72464 MULTI_CORE_FRONT_END TinyAcc showing issues in passing parameter types
AVSREQ-72267 MSIE_ELAB Move partitioning point earlier in the elaborator
AVSREQ-72214 GLS_GENERAL Disable out of scope SDF matching
AVSREQ-72135 VPI_GENERAL 2159956 CCR Xcelium 19.07.001 - Agile release: uvm_reg peek on register field is not returning the proper value
AVSREQ-72038 MSIE_ELAB Instance path terminating in its own primary hierarchy resulting into error DYNGHE
AVSREQ-71786 MSIE_SIMULATION Support VTW in All MSIE flows - Sanity checker
AVSREQ-71361 CORE_PARSE_SV 1960949 CCR Unexpected DEFFIN in assert final
AVSREQ-71311 VPI_GENERAL 2145158 CCR event_port on logic array triggers wrong events
AVSREQ-71084 JUPITER_ENGINE Hydra BDA subsystem: perf analysis with Jupiter in PATPG sim zero delay
AVSREQ-71080 JUPITER_ENGINE Hydra ADC subsystem: perf analysis with Jupiter in PATPG zero delay
AVSREQ-71031 JUPITER_ENGINE Hydra DAC subsystem: perf analysis with JUPITER in PATPG
AVSREQ-70761 JUPITER_BUGS Sim mismatches on Parallel ATPG simulation in zero delay
AVSREQ-70614 MULTI_CORE_FRONT_END Static Elaboration taking 85% of interpreter time
AVSREQ-70417 MULTI_CORE_COMPILER South tool failure when adding debug switches
AVSREQ-69652 VPI_GENERAL 2136007 CCR Memory leak on specman interface with SystemVerilog array of wires
AVSREQ-69516 CORE_PARSE_SV 2119555 CCR instance with assertion coverage marked as n/a
AVSREQ-68863 CORE_PARSE_SV CCR 2040834 : INT_LKFC: xmvlog: *E,EXPIDN (xc_work/v/1n.sv,18|17): expecting an identifier [3.2][3.8][3.9(IEEE)].
AVSREQ-67947 JUPITER_ENGINE Internal simulation error on G2020
AVSREQ-66536 VHDL_GENERAL Enhancement to array aggregates in actual associated with formal port (or members thereof)
AVSREQ-62797 RAND_SOLVER 2035596 CCR support limitation of putting rand in array index in constraint


CCRID Product Title
-------- ------------ ---------------------------
AVSREQ-126730 GLS_TIMING negative offsets in $nochange checks do not seem to be honored
AVSREQ-125666 COVERAGE_CODE set_com output is different for different ways of assignment of std_logic_Vector
AVSREQ-125395 DMS_LICENSE Low Power requires DMSO if vhdl real port
AVSREQ-124785 IP_PROTECT_GENERAL Xmprotect encrypts design with INVALID_INPUT_KEY as key_name for IP-1735 protection
AVSREQ-123970 SIM_CAPTURE_REPLAY XMReplay: XMREPLAY_NORMALIZE_TIME is not working as expected
AVSREQ-123820 SIM_TCL Tcl function returns different outputs from same expression call
AVSREQ-123652 ELAB_SV Add support for genvar as an argument of $bits in constant expression to 20.03 main
AVSREQ-123356 SV_GENERAL [$sformatf] Escape string %% doesn't become % character.
AVSREQ-123346 IP_PROTECT_GENERAL -vlogcontrolrelax NOTDOT is causing strange error in encrypted files
AVSREQ-122821 SIM_VCD XCELIUM 20.03, 20.06 crash while VCD $dumpoff
AVSREQ-122448 ASSERTION_DOC Turning assertion off with wildcard - documentation
AVSREQ-122251 SV_GENERAL psprintf not recognizing values passed with %%d when it calls through $value$plusargs
AVSREQ-122170 ELAB_VHDL xmelab INTERR: cu_cstinit_to - not record
AVSREQ-122006 GLS_SDF Elaboration hang during SDF annotation
AVSREQ-121052 CORE_RAND constraint randomization failing in new version(20.03.002p1)
AVSREQ-120152 SV_CODEGEN xmvlog_cg: *F,INTERR: INTERNAL EXCEPTION gq_tldtoi - wx/wy mismatch
AVSREQ-119997 SV_CODEGEN INTERR MESSAGE: gq_tldtoi - wx/wy mismatch , for RTL setup
AVSREQ-119275 SIM_CAPTURE_REPLAY Checking inputs and Replaying triggers a lot of RPLVALM
AVSREQ-117733 SIM_SAIF_TCF SAIFNSUPP triggered when lps_analyze option is used
AVSREQ-114250 COVERAGE_CODE coverage is not collected for signal for which they should be
AVSREQ-108702 XRUN_GENERAL Reason behind re-elaboration
AVSREQ-100576 VHDL_PARSE apx error when using in VHDL configuration
AVSREQ-94100 DMS_LICENSE DMSO license will be checked out just by adding lps_1801

========
CCRID Product Title
-------- ------------ ---------------------------
JIRA ID COMPONENT SUMMARY
AVSREQ-143994 LP_DOC Fix doc w.r.t. -pg_type in SPA
-------+------+-------------------------------------- -------+------+--------------------------------------
AVSREQ-134517 LP_DOC is_level_shifter (ieee 1801) vs. is_level_shifter_cell (cadence) attribute
Cadence's Xcelium Logic Simulationprovides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company's Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Accelerating DFT Simulations with Xcelium Multi-Core
Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadenceis a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world's most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.


Base_XCELIUMMAIN20.03.001_lnx86
Hotfix_XCELIUMMAIN20.03.010_lnx86
Hotfix_XCELIUMLEGACY20.03.017_lnx86
XCELIUM is simply a newer generation of the digital functional verification tools. Older versions were called INCISIVE. The last INCISIVE version was the 15.20 release, and there have been several XCELIUM releases since then. If using INCISIVE, you'd need to use "ncvhdl" instead of "xmvhdl".




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