Spintronic Microprocessor Architectures for Neuromorphic AI Computing Leveraging Magnetic Phenomena Beyond CMOS Scaling Limits [#1041500]

Spintronic Microprocessor Architectures for Neuromorphic AI Computing: Leveraging Magnetic Phenomena Beyond CMOS Scaling Limits
English | May 19, 2026 | ASIN: B0H29MBV1D | 459 pages | Epub | 1.57 MB
The continued exponential growth of artificial intelligence (AI) workloads has outpaced the energy-efficiency gains available from conventional complementary metal-oxide-semiconductor (CMOS) scaling, producing a memory wall and a power wall that constrain both data-center and edge deployment of neural networks. Spintronic devices, particularly spin-transfer torque magnetoresistive random access memory (STT-MRAM), spin-orbit torque MRAM (SOT-MRAM), and stochastic magnetic tunnel junctions configured as probabilistic bits (p-bits), offer non-volatility, sub-nanosecond switching, and intrinsic radiation hardness that may simultaneously address these limitations. The purpose of this quantitative quasi-experimental dissertation was to design and evaluate a unified spintronic microprocessor architecture for neuromorphic AI computing and to quantify its energy efficiency, write performance, probabilistic inference capability, and radiation tolerance relative to CMOS baselines. A four-tier multi-scale simulation methodology was implemented, comprising OOMMF and MuMax3 micromagnetic modeling of the Landau-Lifshitz-Gilbert-Slonczewski equation, HSPICE circuit simulation with Monte Carlo process variation, NeuroSim and a custom compute-in-memory (CIM) simulator for array-level analysis, and PyNN/NEST spiking neural network evaluation at the 45 nm technology node, encompassing 2,847 independent simulation runs. Four research questions addressed energy efficiency, hybrid SOT-STT switching, p-bit Bayesian inference, and radiation tolerance, each with preregistered hypotheses and corresponding statistical tests. Results demonstrated a 5.92x improvement in tera-operations per second per watt (TOPS/W) for SOT-MRAM CIM over SRAM CIM (RQ1), a 75.3% write energy reduction with a concurrent 50x endurance improvement under hybrid SOT-STT switching (RQ2), a 13.6x energy advantage of p-bit Bayesian inference over digital CMOS implementations (RQ3), and the maintenance of 93.82% inference accuracy at 10 Mrad(Si) total ionizing dose with a 263x improvement in single-event-upset critical charge (RQ4). A radiation-hardened-by-design spintronic architecture achieved 28.4 TOPS/W-a 3.64x improvement over unhardened SRAM CIM-at a 2.1x MRAM CIM area overhead, with analog-to-digital conversion identified as the dominant remaining energy consumer. These findings provide theoretical, methodological, and practical contributions to the design of energy-efficient, fault-tolerant, uncertainty-aware AI accelerators for terrestrial edge, automotive, aerospace, and space applications.