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Mentor Graphics HDL Designer Series (HDS) 2021.1 Build 1



Mentor Graphics HDL Designer Series (HDS) 2021.1 Build 1
Mentor Graphics HDL Designer Series (HDS) 2021.1 | 743.9 mb
Product:Mentor Graphics HDL Designer Series (HDS)
Version:2021.1 build 1
Supported Architectures:x64
Website Home Page :
www.mentor.com

Languages Supported:english
System Requirements:PC *
Size:743.9 mb

The software developer Mentor Graphics, is pleased to announce the availability of HDL Designer Series (HDS) 2021.1 is a powerful HDL-based environment used by individual engineers and engineering teams worldwide to analyze, create and manage complex FPGA and ASIC designs.


What's New in HDL Designer Series 2021.1 - Date: January 2021
The v2021.1 release includes the following new features and enhancements.
HDL Designer
- Subversion Rollback support
- Xilinx Vivado 2020.2 support
- Intel Quartus Prime 20.1 Standard Edition support
SystemVerilog -VHDL Assistant
- General performance and stability improvement
- Xilinx Vivado 2020.2 support
Register Assistant
- Multiple address block support in IP-XACT register definitions
External Tool Support
The HDL Designer Series tool interfaces have been tested with certain external tool versions. Some tools may not be available on all platforms.
Downstream Tools

Tools Discontinued
The following version management interfaces are no longer supported
- ClioSoft SOS
- GNU Revision Control System (RCS)
- Microsoft or Mainsoft Visual SourceSafe (VSS)
Java Runtime Environment
SystemVerilog-VHDL Assistant and Register Assistant run on OpenJDK JRE 8u252.
Software Version 2021.1
Refer to the list of issues and enhancements that have been addressed in the v2021.1 release

HDL Designer
- HDS-14789 - Request to provide a script that checks missing fonts and libraries on Linux.
- HDS-21315 - Request to support soft paths in the Questa replay script.
- HDS-21374 - Request to fix an issue in which the Questa compilation creates an extra folder in the Downstream directory. This issue occurs when setting the MODELSIM environment variable.
- HDS-21487 - Request to support the Subversion Rollback operation.
- HDS-21493 - Request to decouple the HDS flows from the Questa library directory.
- HDS-21506 - Request to fix an issue in which the option "Generate 'End' statement for frames" causes incorrect VHDL generation.
- HDS-21519 - Request to enhance a Questa warning indicating that the global +acc is enabled automatically, thus slowing the simulation process.
- HDS-21520 - Request to enhance the Xilinx Vivado flow to recognize IPs that use the uppercase and mixed-case letters.
- HDS-21531 - Request to enable the Xilinx Vivado flow to accept environment variables for the Compiled Vendor Library directory.
- HDS-21536 - Request to provide an API command for the FPGA Library Compile task.
- HDS-21538 - Request to enhance the approach used by the Subversion Update and Rollback operations to handle conflicts in graphical design units.
- HDS-21540 - Request to fix an incorrect reference in the Graphical Editors User Manual.
- HDS-21542 - Request to fix an issue in which the Xilinx Vivado tasks delete all side data, including user-added data.
- HDS-21551 - Request to support importing selected Xilinx Vivado cores.
- HDS-21552 - Request to fix an issue in which a missing simulator path causes downstream problems.
- HDS-21553 - Request to display the Questa compiler error "vcom-153" in red text color in the HDS Log window.
- HDS-21564 - Request to support importing IPs using the "copy mode" when using Xilinx Vivado 2020.2.
- HDS-21569 - Request to support Quartus Prime Standard Edition 20.1.
- HDS-21573 - Request to update the FPGA devices required to support Quartus Prime Standard Edition 20.1.
DesignChecker
- DC-2284 - Request to fix a segmentation violation raised during the DesignChecker analysis of a specific design.
- DC-2292 - Request to update the supported languages of base rules in the Base Rules
Reference Guide
- DC-2299 - Request to fix an incorrect syntax error raised on running DesignChecker analysis in batch mode while setting the -top option.
- DC-2300 - Request to fix incorrect unbound component messages for generated VHDL code.
SystemVerilog-VHDL Assistant
- SVVA-4377 - Request to support filtering library names in the Import From Questa dialog box.
- SVVA-4430 - Request to fix the ability to cancel a running Questa build operation.
- SVVA-4474 - Request to apply operations to the correct project when two projects are open in SystemVerilog-VHDL Assistant.
- SVVA-4476 - Request to fix the importDesignFromQuestaIniFile API command to be consistent with the GUI operation.
- SVVA-4477 - Request to fix a crash that occurs on exiting SystemVerilog-VHDL Assistant while running a visualization operation.
- SVVA-4486 - Request to maintain the consistency between the Verilog/SystemVerilog macro definitions and the project build defines.
- SVVA-4489 - Request to fix a crash that occurs on running some API commands in the console.
- SVVA-4494 - Request to fix the ability to set the default top for VHDL designs when using the API command.
- SVVA-4508 - Request to enhance the performance of the browser filtering capability with large Verilog designs.
Register Assistant
- RA-449 - Request to set the word addressing feature when addressUnitBits is definedin the IP-XACT input.
- RA-500 - Request to fix a C Header generation failure that occurs with an IP-XACT 2009 file.
- RA-505 - Request to support multiple address blocks in IP-XACT register definitions

HDL Designeris a powerful HDL-based environment which delivers new approaches to design today's most complex FPGAs and ASICs. HDL Designer is used worldwide by individual engineers and engineering teams to create, analyze and manage the design of these amazing devices.
HDL Designer accelerates the productivity and predictability of the project by automating many flows and tasks. Automated rule checking, register generation and documentation and the powerful text, tabular and graphical creation editors save incredible amounts of engineering time and can minimize manually introduced errors. Tool integration and version management of the entire project help keep the team, tools and design process structured, but is still flexible enough through an API to augment existing design flows. Through this automation and project management, the overall quality of the project and resulting chip is improved and project risk greatly reduced.
By using HDL Designer, savings and cost avoidance can be recognized immediately through this automation and will continue with future projects through better design reuse, consistency of coding and improved documentation. For safety- and mission-critical projects, HDL Designer's design checking, version management, register generation and documentation support adherence to regulatory compliance mandates such as DO-254 and ISO 26262.
Mentor graphics : Block Diagram design in HDL Designer
Mentor Graphics Corporation, a Siemens business,is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Product:Mentor Graphics HDL Designer Series (HDS)
Version:2021.1 build 1
Supported Architectures:x64
Website Home Page :
www.mentor.com

Languages Supported:english
System Requirements:PC *
Size:743.9 mb



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